This is the instruction set which is implemented by the MCSIM simulator which comes with Archelon's tools. The sample CIF file generates instructions in this set. Many instructions have an extension suffix, which tells us about the type and/or the location of the operation to be performed.
The list of extensions is
| b | - byte; |
| w | - word; |
| l | - long word; |
| f | - float; |
| d | - double; |
| u | - unsigned (used only for branch instructions) |
In order to save space, an instruction which can have several different extensions is shown as one instruction with the various possible extensions separated by or-bars. For instance, if there is an instruction called ``rdimm'' which is used for ``l'', ``w'', or ``d'' extensions, then we will show it as
rdimm_l|w|d
which means we can have one of
rdimm_l
rdimm_w
rdimm_d
We will show the list of instructions grouped into the following categories.
ldzi_b|w|l|f|d address,dst_reg
- load from direct address
- byte and word loads sign extend
lduzi_b|w address,dst_reg
- unsigned load from direct address
ldri_b|w|l|f|d addr_reg,offset_val,dst_reg
- load from *(addr_reg + offset_val)
- byte and word loads sign extend
lduri_b|w addr_reg,offset_val,dst_reg
- unsigned load from *(addr_reg + offset_val)
ldrr_b|w|l|f|d addr_reg,offset_reg,dst_reg
- load from *(addr_reg + offset_reg)
- byte and word loads sign extend
ldrr_b|w addr_reg,offset_reg,dst_reg
- unsigned load from *(addr_reg + offset_reg)
strzi_b|w|l|f|d src_reg,address
- store register at direct address
stizi_b|w|l|f|d imm_val,address
- store immediate at direct address
strri_b|w|l|f|d src_reg,addr_reg,offset_val
- store register at *(addr_reg + offset_val)
stiri_b|w|l|f|d imm_val,addr_reg,offset_val
- store immediate at *(addr_reg + offset_val)
strrr_b|w|l|f|d src_reg,addr_reg,offset_reg
- store register at *(addr_reg + offset_reg)
stirr_b|w|l|f|d imm_val,addr_reg,offset_reg
- store immediate at *(addr_reg + offset_reg)
(45 possible)
ldzi2_b|w|l|f|d address,dst_reg
- load from direct address
ldri2_b|w|l|f|d addr_reg,offset_val,dst_reg
- load from *(addr_reg + offset_val)
ldrr2_b|w|l|f|d addr_reg,offset_reg,dst_reg
- load from *(addr_reg + offset_reg)
strzi2_b|w|l|f|d src_reg,address
- store register at direct address
stizi2_b|w|l|f|d imm_val,address
- store immediate at direct address
strri2_b|w|l|f|d src_reg,addr_reg,offset_val
- store register at *(addr_reg + offset_val)
stiri2_b|w|l|f|d imm_val,addr_reg,offset_val
- store immediate at *(addr_reg + offset_val)
strrr2_b|w|l|f|d src_reg,addr_reg,offset_reg
- store register at *(addr_reg + offset_reg)
stirr2_b|w|l|f|d imm_val,addr_reg,offset_reg
- store immediate at *(addr_reg + offset_reg)
(45 possible)
mov_w|l|f|d src_reg,dst_reg
- dst_reg = src_reg
movi_w|l|f imm_val,dst_reg
- dst_reg = imm_val
add_w|l|f|d lop_reg,rop_reg,dst_reg
- dst_reg = lop_reg + rop_reg
addi_w|l|f lop_reg,imm_val,dst_reg
- dst_reg = lop_reg + imm_val
sub_w|l|f|d lop_reg,rop_reg,dst_reg
- dst_reg = lop_reg - rop_reg
subi_w|l|f lop_reg,imm_val,dst_reg
- dst_reg = lop_reg - imm_val
mul_w|l|f|d lop_reg,rop_reg,dst_reg
- dst_reg = lop_reg * rop_reg
muli_w|l|f lop_reg,imm_val,dst_reg
- dst_reg = lop_reg * imm_val
mulu_w|l lop_reg,rop_reg,dst_reg
- dst_reg = lop_reg * rop_reg (unsigned)
mului_w|l lop_reg,imm_val,dst_reg
- dst_reg = lop_reg * imm_val (unsigned)
div_w|l|f|d lop_reg,rop_reg,dst_reg
- dst_reg = lop_reg / rop_reg
divi_w|l|f lop_reg,imm_val,dst_reg
- dst_reg = lop_reg / imm_val
divu_w|l lop_reg,rop_reg,dst_reg
- dst_reg = lop_reg / rop_reg (unsigned)
divui_w|l lop_reg,imm_val,dst_reg
- dst_reg = lop_reg / imm_val (unsigned)
mod_w|l lop_reg,rop_reg,dst_reg
- dst_reg = lop_reg % rop_reg
modi_w|l lop_reg,imm_val,dst_reg
- dst_reg = lop_reg % imm_val
modu_w|l lop_reg,rop_reg,dst_reg
- dst_reg = lop_reg % rop_reg (unsigned)
modui_w|l lop_reg,imm_val,dst_reg
- dst_reg = lop_reg % imm_val (unsigned)
and_w|l lop_reg,rop_reg,dst_reg
- dst_reg = lop_reg & rop_reg
andi_w|l lop_reg,imm_val,dst_reg
- dst_reg = lop_reg & imm_val
or_w|l lop_reg,rop_reg,dst_reg
- dst_reg = lop_reg | rop_reg
ori_w|l lop_reg,imm_val,dst_reg
- dst_reg = lop_reg | imm_val
xor_w|l lop_reg,rop_reg,dst_reg
- dst_reg = lop_reg ^ rop_reg
xori_w|l lop_reg,imm_val,dst_reg
- dst_reg = lop_reg ^ imm_val
lls_w|l lop_reg,rop_reg,dst_reg
- dst_reg = lop_reg << rop_reg (zero fill)
llsi_w|l lop_reg,imm_val,dst_reg
- dst_reg = lop_reg << imm_val (zero fill)
ars_w|l lop_reg,rop_reg,dst_reg
- dst_reg = lop_reg >> rop_reg (sign fill)
arsi_w|l lop_reg,imm_val,dst_reg
- dst_reg = lop_reg >> imm_val (sign fill)
lrs_w|l lop_reg,rop_reg,dst_reg
- dst_reg = lop_reg >> rop_reg (zero fill)
lrsi_w|l lop_reg,imm_val,dst_reg
- dst_reg = lop_reg >> imm_val (zero fill)
cmp_w|l|f|d lop_reg,rop_reg
- comparative subtract
(lop_reg - rop_reg)
to set
condition codes
cmpu_w|l lop_reg,rop_reg
- comparative unsigned subtract
(lop_reg - rop_reg)
to set condition codes
cmpi_w|l|f lop_reg,imm_val
- comparative subtract immediate
(lop_reg - imm_val)
to set condition codes
cmpui_w|l lop_reg,imm_val
- comparative unsigned subtract
immediate (lop_reg - imm_val)
to set condition codes
com_w|l src_reg,dst_reg
- dst_reg = src_reg (one's complement)
neg_w|l|f|d src_reg,dst_reg
- dst_reg = -src_reg (two's complement)
abs_w|l|f|d src_reg,dst_reg
- dst_reg = abs(src_reg) (absolute value)
sqrt_w|l|f|d src_reg,dst_reg
- dst_reg = sqrt(src_reg) (square root)
sqrtu_w|l src_reg,dst_reg
- dst_reg = sqrt(src_reg) (square root unsigned)
(104 possible)
cvtsbw src_reg,dst_reg
- convert signed byte to word
cvtubw src_reg,dst_reg
- convert unsigned byte to word
cvtsbl src_reg,dst_reg
- convert signed byte to long
cvtubl src_reg,dst_reg
- convert unsigned byte to long
cvtswl src_reg,dst_reg
- convert signed word to long
cvtuwl src_reg,dst_reg
- convert unsigned word to long
cvtlw src_reg,dst_reg
- convert long to word
cvtwf src_reg,dst_reg
- convert word to float
cvtuwf src_reg,dst_reg
- convert unsigned word to float
cvtlf src_reg,dst_reg
- convert long to float
cvtulf src_reg,dst_reg
- convert unsigned long to float
cvtdf src_reg,dst_reg
- convert double to float
cvtfw src_reg,dst_reg
- convert float to word
cvtfl src_reg,dst_reg
- convert float to long
cvtfd src_reg,dst_reg
- convert float to double
cvtwd src_reg,dst_reg
- convert word to double
cvtuwd src_reg,dst_reg
- convert unsigned word to double
cvtld src_reg,dst_reg
- convert long to double
cvtuld src_reg,dst_reg
- convert unsigned long to double
cvtdw src_reg,dst_reg
- convert double to word
cvtdl src_reg,dst_reg
- convert double to long
cvtlb src_reg,dst_reg
- convert long to byte
cvtwb src_reg,dst_reg
- convert word to byte
(23 possible)
br address
beq address
beq_f address
bne address
bne_f address
ble address
ble_u|f address
blt address
blt_u|f address
bgt address
bgt_u|f address
bge address
bge_u|f address
bch address
- branch if carry high
bcl address
- branch if carry low
boh address
- branch if overflow high
bol address
- branch if overflow low
bucch immval,address
- branch on user condition code
(selected by immval) high
buccl immval,address
- branch on user condition code
(selected by immval) low
jmpind addr_reg
- jump indirect to
code address in addr_reg
(24 possible)
call address
- call to direct address
callind addr_reg
- call indirect to address in register
ret
- return to caller
enti
- enter interrupt function
reti
- leave interrupt function
(5 possible)
control const
- execute some arbitary operation, selected by "const"
input_b|w|l|f|d const,reg
- receive a value from a port into a register
output_b|w|l|f|d const,reg
- send a value to a port
outputi_b|w|l const,const
- send an immediate value to a port
(14 possible)
loopinit reg,loop_end_label
- load loop counter from a register
loopiniti immval,loop_end_label
- load loop counter with
an immediate value
loophead loop_top_label,loop_end_label
- actions after loop_top_label emitted
loopend loop_top_label,loop_end_label
- actions after loop_end_label emitted
looprpt loop_top_label,loop_end_label
- restart the loop if
the loop counter is not exhausted
loopret
- return from inside a loop
(6 possible)